Vias are routinely used structures in the construction of integrated circuit (IC) devices. By way of example, vias may be used to form electrical connections between various layers of conductors in the interconnect structure of an IC die. By way of further example, vias may also be formed that extend from the backside of an IC die to the active or front side, such vias often referred to as “through-silicon vias.” Through-silicon vias can, for example, be used to form backside interconnects for a pair of bonded wafers, the bonded wafers forming a wafer stack that is ultimately cut into a number of stacked die. In addition, through-silicon vias may also find use in MEMS (Micro-Electromechanical Systems) devices.
Through-silicon vias may be filled with copper or other conductive material to provide for an electrical connection to a circuit from the backside of a die (or wafer). Copper, as well as other conductive metals, has a higher coefficient of thermal expansion (CTE) than silicon. For example, copper has a CTE of approximately 16.5 ppm/° C., whereas silicon has a CTE of approximately 2.6 ppm/° C. This CTE mismatch may result in significant stress in the silicon and copper (or other conductive material) after copper deposition, as well as during any subsequent temperature cycling (e.g., as may occur during solder reflow, during testing, or during use). In addition, when vias are spaced relatively close together such that their stress fields interact, these stresses may be further magnified. The stresses that may result from the above-described CTE mismatch can lead to numerous problems, including thin-film delamination, cracking of the silicon, and reduced transistor performance (any of which may lead to lower yields and reliability failures).
A number of solutions have been proposed to alleviate the effects of CTE mismatches in conductive-filled through-silicon vias. One solution is to make the diameter of the vias smaller in order to reduce the stress from each individual via. Another solution is to position vias far apart from one another to limit the interaction of the stress fields between adjacent vias. A further solution is to position vias far from any active circuitry to ensure stress fields do not penetrate the area proximate the active circuitry. Should the via stress fields penetrate the regions near active circuitry, carrier mobility may be reduced and transistor performance degraded.